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FST16292 12-Bit to 24-Bit Multiplexer/Demultiplexer Bus Switch
July 1997 Revised December 1999
FST16292 12-Bit to 24-Bit Multiplexer/Demultiplexer Bus Switch
General Description
The Fairchild Switch FST16292 provides twelve 2:1 highspeed CMOS TTL-compatible multiplexer/demultiplexer bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The select pin connects the A Port to the selected B Port output. The A2 Ports are not externally connected, thus have a 500 pull-down resistor to ground.
Features
s 4 switch connection between two ports. s Minimal propagation delay through the switch. s Low lCC. s Zero bounce in flow-through mode. s Control inputs compatible with TTL level. s Internal 500 pull-down resistor on A2 port.
Ordering Code:
Order Number FST16292MEA FST16292MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Diagram
Connection Diagram
Pin Descriptions
Pin Name SO A1 B1 , B2 Description Data-select input Bus A Bus B
Truth Table
S0 L H A1 B1 B2 A2 B2 B1 Function A1 = B1 , A2 = B2 A1 = B2 , A2 = B1
(c) 1999 Fairchild Semiconductor Corporation
DS500104
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FST16292
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC ) DC Switch Voltage (VS) DC Input Voltage (VIN) (Note 2) DC Input Diode Current (lIK) VIN<0V DC Output (IOUT ) Sink Current DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) -0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -50mA 128mA +/- 100mA -65C to +150 C
Recommended Operating Conditions
Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Input Rise and Fall Time (tr, tf) Switch Control Input Switch I/O Free Air Operating Temperature (TA) 0ns/V to 5ns/V 0ns/V to DC -40 C to +85 C 4.0V to 5.5V 0V to 5.5V 0V to 5.5V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed.
DC Electrical Characteristics
Symbol VIK VIH VIL II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 4) VCC (V) 4.5 4.0-5.5 4.0-5.5 5.5 0 5.5 4.5 4.5 4.5 4.0 ICC ICC Quiescent Supply Current Increase in ICC per Input 5.5 5.5 4 4 8 14 2.0 0.8 1.0 10 1.0 7 7 12 20 3 2.5 TA = -40 C to +85 C Min Typ (Note 3) Max -1.2 Units V V V A A A A mA 0 VIN 5.5V VIN = 5.5V 0 A, B VCC VIN = 0V, IIN = 64mA VIN = 0V, IIN = 30mA VIN = 2.4V, IIN = 15mA VIN = 2.4V, IIN = 15mA VIN = VCC or GND, IOUT = 0 One input at 3.4V Other inputs at VCC or GND
Note 3: Typical values are at VCC = 5.0V and T A =+25C Note 4: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins.
Conditions IIN = -18mA
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FST16292
AC Electrical Characteristics
TA = -40 C to +85 C, Symbol Parameter CL = 50pF, RU = RD = 500 VCC = 4.5 - 5.5V Min tPHL,tPLH tPHL,tPLH tPZL, tPZH tPLZ, tPHZ Prop Delay Bus to Bus (Note 5) Prop Delay S0 to A1 Output Enable Time S0 to B1 or B2 Output Disable Time S0 to B1 or B2 1.5 Max 0.25 7.0 VCC = 4.0V Min Max 0.25 7.4 ns ns VI = OPEN VI = OPEN VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Figure 1 Figure 2 Units Conditions Figure No.
1.0 1.0
6.7 7.5
7.0 7.8
ns ns
Note 5: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol CIN CI/O
(Note 6)
Parameter Typ 3 10 Max Units pF pF Conditions VCC = 5.0V VCC = 5.0V, S0 =GND
Control pin Input Capacitance Input/Output Capacitance
Note 6: TA = +25C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 source terminated in 50 Note: CL includes load and stray capacitance Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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FST16292
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A
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FST16292 12-Bit to 24-Bit Multiplexer/Demultiplexer Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild's proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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